Divide-by-two quadrature divider circuits are generally used to divide down a high frequency signal generated by a high speed phased-locked loop (“PLL”). PLL devices receive external low frequency clock input signals and utilize those signals to generate high frequency signals. Under normal conditions, the divide-by-two quadrature divider can take true and complement clock signals (i.e. wherein a true signal is transitioning from low to high and a complement signal is transitioning from high to low) as inputs, and provide a first and second pair of true and complement clock signals at the quadrature divider's outputs, wherein the first pair and second pair provide one-half the input frequency of the quadrature divider, and wherein the second pair has a 90 degree phase difference with respect to the first pair.
However, a divide-by-two quadrature divider circuit is susceptible to metastability when operating with high frequency signals. Specifically, current design topology for a divide-by-two quadrature divider, utilized in dividing down PLL output frequency, can result in the output of the divide-by-two quadrature divider entering into and remaining in a metastable state. Generally, metastability at the output of the divide-by-two quadrature divider occurs during startup or initial settling time while the PLL is operating at high frequency application (for example, when PLL output frequency is greater than approximately 25 GHz). A divide-by-two quadrature divider will receive a pair of clock input signals at a given frequency at its input, and generate a first and second pair of output signals that are one-half the frequency of the clock input signals' frequency. Moreover, the second pair of output signals will have a 90 degree phase difference with respect to the first pair of output signals. However, when metastability occurs the divide-by-two quadrature divider's output signals will not reach rail-to-rail (i.e. reach Vdd or Vss), the output signals will not be true and complement, and the output signals will not have the expected phase differences with respect to the clock input signals. An object of the present invention is to resolve such metastability with minimal impact on circuit topology and on power consumption.